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Fixed-Point Digital Signal Processor 的TMS32C6414EZLZ6E3
Click and browse the big picture of product Fixed-Point Digital Signal Processor 的TMS32C6414EZLZ6E3!
【Product name】 Fixed-Point Digital Signal Processor 的TMS32C6414EZLZ6E3
【Product categories】 IC
【Market price】 
【Price of this website】 Promotion 特价
【Product usage】 Fixed-Point Digital Signal Processor
【Product spec】 pack: 532-pin plastic BGA, Pb−free soldered balls
【Mfg】 TI (德州仪器)
【Product instruction】 TMS32C6414EZLZ6E3  240pcs  2007+    new! Original ! Stock! 

Description

The TMS320C64x™ DSPs (including the TMS320C6414, TMS320C6415, and TMS320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™ developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges.

View full Description in Datasheet

Features

Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
2-, 1.67-, 1.39-ns Instruction Cycle Time
500-, 600-, 720-MHz Clock Rate
Eight 32-Bit Instructions/Cycle
Twenty-Eight Operations/Cycle
4000, 4800, 5760 MIPS
Fully Software-Compatible With C62x™
C6414/15/16 Devices Pin-Compatible
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
Non-Aligned Load-Store Architecture
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear

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【Update date】 2014/3/24 19:01:37
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